So I updated the script to
s905x3 with L2 cache
#!/bin/sh
(
/bin/mount -o rw,remount /flash
fdtput -p /flash/dtb.img /cpus/l3-cache0 compatible cache -t s
fdtput -p /flash/dtb.img /cpus/l3-cache0 cache-level 3 -t i
fdtput -p /flash/dtb.img /cpus/l3-cache0 cache-unified
fdtput -p /flash/dtb.img /cpus/l3-cache0 cache-size 0x7d000 -t x
fdtput -p /flash/dtb.img /cpus/l3-cache0 cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/l3-cache0 cache-sets 512 -t i
fdtput -p /flash/dtb.img /cpus/l3-cache0 phandle 1113 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache0 compatible cache -t s
fdtput -p /flash/dtb.img /cpus/l2-cache0 cache-level 2 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache0 cache-size 0x10000 -t x
fdtput -p /flash/dtb.img /cpus/l2-cache0 cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache0 cache-sets 512 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache0 next-level-cache 1113 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache0 phandle 1114 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache1 compatible cache -t s
fdtput -p /flash/dtb.img /cpus/l2-cache1 cache-level 2 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache1 cache-size 0x10000 -t x
fdtput -p /flash/dtb.img /cpus/l2-cache1 cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache1 cache-sets 512 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache1 next-level-cache 1113 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache1 phandle 1115 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache2 compatible cache -t s
fdtput -p /flash/dtb.img /cpus/l2-cache2 cache-level 2 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache2 cache-size 0x10000 -t x
fdtput -p /flash/dtb.img /cpus/l2-cache2 cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache2 cache-sets 512 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache2 next-level-cache 1113 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache2 phandle 1116 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache3 compatible cache -t s
fdtput -p /flash/dtb.img /cpus/l2-cache3 cache-level 2 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache3 cache-size 0x10000 -t x
fdtput -p /flash/dtb.img /cpus/l2-cache3 cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache3 cache-sets 512 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache3 next-level-cache 1113 -t i
fdtput -p /flash/dtb.img /cpus/l2-cache3 phandle 1117 -t i
fdtput -p /flash/dtb.img /cpus/cpu@0 compatible "arm,cortex-a55" "arm,armv8" -t s
fdtput -p /flash/dtb.img /cpus/cpu@0 d-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@0 d-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@0 d-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@0 i-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@0 i-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@0 i-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@0 next-level-cache 1114 -t i
fdtput -p /flash/dtb.img /cpus/cpu@1 compatible "arm,cortex-a55" "arm,armv8" -t s
fdtput -p /flash/dtb.img /cpus/cpu@1 d-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@1 d-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@1 d-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@1 i-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@1 i-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@1 i-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@1 next-level-cache 1115 -t i
fdtput -p /flash/dtb.img /cpus/cpu@2 compatible "arm,cortex-a55" "arm,armv8" -t s
fdtput -p /flash/dtb.img /cpus/cpu@2 d-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@2 d-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@2 d-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@2 i-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@2 i-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@2 i-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@2 next-level-cache 1116 -t i
fdtput -p /flash/dtb.img /cpus/cpu@3 compatible "arm,cortex-a55" "arm,armv8" -t s
fdtput -p /flash/dtb.img /cpus/cpu@3 d-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@3 d-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@3 d-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@3 i-cache-line-size 64 -t i
fdtput -p /flash/dtb.img /cpus/cpu@3 i-cache-size 0x8000 -t x
fdtput -p /flash/dtb.img /cpus/cpu@3 i-cache-sets 32 -t i
fdtput -p /flash/dtb.img /cpus/cpu@3 next-level-cache 1117 -t i
/bin/sync
/bin/mount -o ro,remount /flash
read -p "Restart now? [Y/N]: " KEYINPUT
if [ "$KEYINPUT" != "${KEYINPUT#[Yy]}" ]; then
/sbin/reboot
fi
)
@rho-bot is that how it should be?
and am now getting
CoreELEC-21:~ # lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Vendor ID: ARM
Model name: Cortex-A55
Model: 0
Thread(s) per core: 1
Core(s) per cluster: 4
Socket(s): -
Cluster(s): 1
Stepping: r1p0
CPU(s) scaling MHz: 100%
CPU max MHz: 1908.0000
CPU min MHz: 100.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp asimddp
Caches (sum of all):
L1d: 128 KiB (4 instances)
L1i: 128 KiB (4 instances)
L2: 2 MiB (4 instances)
CoreELEC-21:~ # lscpu --caches
NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE
L1d 32K 128K 4 Data 1 128 64
L1i 32K 128K 4 Instruction 1 128 64
L2 512K 2M 16 Unified 2 512 64
To get the 2MB is it counting the 512 KB L3 four times?