I think you are right about the separate L2 caches for the two clusters. The wording in the s922x datasheet is just clumsy. The A311D2 datasheet is more clear
The main system CPU is based on Big.LITTLE architecture which integrates a quad-core ARM Cortex-A73 CPU cluster and a quad-core Cortex-A53 cluster with unified L2 cache for each cluster to improve system performance. In addition, the CPU includes the NEON SIMD co-processor to improve software media processing capability.
And also
- Unified system L2 cache for each cluster
The same optimization would also benefit other big little core SOCs like the A311D2, and maybe the S928X (no datasheet available yet). But again the A311D2 datasheet doesn’t specify the L2 cache sizes.