any chance you can test the single core and multicore speed compared to your x96 box you got, I’m real curious on how close we are to the leading CPU. This isn’t even the finalised stuff, trading heat for more performance is a possibility! so excited. CoreELEC has come out with DV, FEL, work by CPM. this community rocks. thanks everyone!
Thanks for pointing out the HS200.
For others: Do not delete the xml if you don’t want to.
I was doing A/B testing and that’s why I deleted my xml.
I wouldn’t expect any benchmark numbers on 922X to beat out 928X.
1 Like
I deleted my xml but backed it up first. Should I restore it? Does it make a difference?
No difference. Just make sure you are using HS400.
thank you for sharing with us, could you see if it changed and worked?
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 6
On-line CPU(s) list: 0-5
Vendor ID: ARM
Model name: Cortex-A53
Model: 4
Thread(s) per core: 1
Core(s) per socket: 2
Socket(s): 1
Stepping: r0p4
CPU(s) scaling MHz: 100%
CPU max MHz: 1800.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32
Model name: Cortex-A73
Model: 2
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
Stepping: r0p2
CPU(s) scaling MHz: 100%
CPU max MHz: 2208.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32
Through new cpu government ? Now are ondemand and performance. Maybe as “mode for cpu with fan” ? Temperature is very important for these small boxes from side their durability and for also stability during gaming. Performance mode is now good for game playing in retroarch (e.g. flycast), please dont touch this mode. Mayby higher ratio of A73 would be help, but please must tested carefully from side of using in retroarch.
I do not see cache information. The DTB didn’t work.
would you be plz explain to me how? I tried and read the whole thread and I followed these steps: I downloaded the file for am6b then I renamed to dtb.img then I copied it to /flash directory and I rebooted am6b, if there are some missing please point me in the right direction. thank you.
You did all the steps. I’m at a loss of words.
Can’t say what’s gone wrong, just overwrite the DTB.img one more time and make sure there is no update in the .update folder.
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Any knowledge / insight on why a tar update would overwrite the dtb.img, would have thought that was one a one time install only, and how would it know which dtb to use.
I mention because I swapped out this morning and then ran an update tar to check what would happen and it did look like it reverted (based on file size).
1 Like
The dtb is updated also, there are changes to the dtb when needed.
2 Likes
Massive increase in responsiveness especially around widgets running Arctic Fuse. You’ve truly unlocked significant performance gains. Well done.
1 Like
great news! can you share the hardware you are using?
also if you are in a position could you (as kindly requested by the Developer)
All DTB files with g12b. Please report back with your findings of lscpu and cpu usage. Data and metrics are preferred.
For e.g. using software decode VC-1 used to consume 50% CPU across cores 0-5 but after update it consumes 20% on core 0-1 and 65% on core 2-5. Something like this is ideal if you are able to get data like that.
Complete quantified data can be had if there are perf binaries compiled for CE-NG.
would be greatly appreciated thanks
@MasterKeyxda
I, did my testing with my AM6B+ unit and got similar results.
I use an AM6B+ with the n Version of the firmware of the 0.5.4 software, the only info the ugoos sites says about that is “add new ddr chip models support” so my model might have some other ram chips installed? I’m not sure, if this makes a big difference in performance.
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 6
On-line CPU(s) list: 0-5
Vendor ID: ARM
Model name: Cortex-A53
Model: 4
Thread(s) per core: 1
Core(s) per socket: 2
Socket(s): 1
Stepping: r0p4
CPU(s) scaling MHz: 100%
CPU max MHz: 1800.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32
Model name: Cortex-A73
Model: 2
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
Stepping: r0p2
CPU(s) scaling MHz: 100%
CPU max MHz: 2208.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32
L1d cache: 192 KiB (6 instances)
L1i cache: 320 KiB (6 instances)
L2 cache: 1.3 MiB (2 instances)
lscpu-caches
NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE
L1d 32K 192K 4 Data 1 128 64
L1i 32K 320K 2 Instruction 1 256 64
L2 256K 1.3M 16 Unified 2 256 64
Another - sample H264 Hi10P 720p avi
top - 20:57:40 up 20 min, 1 user, load average: 0.93, 1.39, 0.77
Tasks: 184 total, 3 running, 181 sleeping, 0 stopped, 0 zombie
%Cpu0 : 17.1 us, 7.0 sy, 0.0 ni, 75.8 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu1 : 25.9 us, 1.0 sy, 0.0 ni, 73.1 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu2 : 23.6 us, 0.0 sy, 0.0 ni, 76.4 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu3 : 1.3 us, 1.0 sy, 0.3 ni, 97.4 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu4 : 0.0 us, 0.0 sy, 0.0 ni,100.0 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu5 : 1.0 us, 0.0 sy, 0.0 ni, 99.0 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
MiB Mem : 3799.5 total, 2849.8 free, 600.1 used, 432.6 buff/cache
MiB Swap: 0.0 total, 0.0 free, 0.0 used. 3199.4 avail Mem
Another - sample H264 Hi10P 1080p avi
top - 20:59:02 up 21 min, 1 user, load average: 1.03, 1.29, 0.79
Tasks: 181 total, 1 running, 180 sleeping, 0 stopped, 0 zombie
%Cpu0 : 6.0 us, 0.7 sy, 0.0 ni, 93.3 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu1 : 5.7 us, 3.7 sy, 0.0 ni, 90.6 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu2 : 55.8 us, 1.7 sy, 0.0 ni, 42.2 id, 0.0 wa, 0.0 hi, 0.3 si, 0.0 st
%Cpu3 : 62.3 us, 1.0 sy, 0.0 ni, 36.8 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu4 : 38.1 us, 2.3 sy, 0.0 ni, 59.5 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu5 : 41.4 us, 3.3 sy, 0.3 ni, 55.0 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
MiB Mem : 3799.5 total, 2654.8 free, 795.0 used, 432.7 buff/cache
MiB Swap: 0.0 total, 0.0 free, 0.0 used. 3004.5 avail Mem
1080p AV1 - 1800Kb/s (constant bitrate)
top - 21:11:51 up 34 min, 1 user, load average: 2.81, 3.31, 2.34
Tasks: 181 total, 1 running, 180 sleeping, 0 stopped, 0 zombie
%Cpu0 : 61.0 us, 8.1 sy, 0.0 ni, 30.8 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu1 : 61.2 us, 6.0 sy, 0.3 ni, 32.4 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu2 : 26.6 us, 1.7 sy, 0.0 ni, 71.7 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu3 : 19.3 us, 0.3 sy, 0.0 ni, 80.3 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu4 : 18.3 us, 1.0 sy, 0.0 ni, 80.7 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
%Cpu5 : 15.0 us, 1.7 sy, 0.0 ni, 83.3 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
MiB Mem : 3799.5 total, 2619.7 free, 829.4 used, 433.4 buff/cache
MiB Swap: 0.0 total, 0.0 free, 0.0 used. 2970.1 avail Mem
Hi10P files are always software decoded. Hi10P files are from the Kodi samples wiki Page.
I guess AV1 with 2000Kb/s constant bitrate should also work, but I’m not totally sure about that. All numbers are with the new “g12b_s922x_ugoos_am6b_all.dtb”
It’s a definite boost in performance compared to before.
Great work @MasterKeyxda! 
2 Likes
Thank you so much for the data and tables. I ran a 20MB 10s AV1 1080p file no problem. If my math is right it is a 20*8/10 = 16 Mbps, your file is 1.8 Mbps and I can see that your A53 cluster is doing most of the work keeping CPU temps low and generally extracting the most out of big.little.
My 16 Mbps file runs the A73 cluster at max and A53 stays in the background.
I have not heard a single complaint about this change yet. I am satisfied with testing performed on this so far.
I have built devices for automotive certifications and my mental model around longevity wouldn’t let me push a code out that could damage internals. A hot CPU isn’t the end of the world because CPUs can handle the temps very well, its the other circuitry around it that suffers. The capacitors nearby may degrade over time due to elevated temps (have done accelerated tests on closed IP69K devices where that was a problem). I don’t want to push the envelope of thermals too far.
The change will be submitted as is, including the incorrect cache size. Can always do a PR in the future and revert some dumb mistake I made.
6 Likes
just amazing work, we really appreciate you going the extra steps to get this into CoreELEC, feels like the days people could unlock cores on their CPU!
Am6b+. Don’t really have time right now to provide performance data. Plenty of others already have. It’s pretty conclusive that the alterations are positive.
2 Likes
I followed the above steps then I run the command:
CoreELEC:~ # mount -o remount,rw /flash
mv dtb.img dtb_o.img
mv: can’t rename ‘dtb.img’: No such file or directory
g12b_s922x_ugoos_am6b_all.dtb (74.1 KB)
Attachment removed! It will be available in nightly build!
this the file I used.
cd /flash
You have to enter the /flash directory