[    0.803192@0] meson-mmc: emmc: resp_timeout,vstat:0x9dff0800,virqc:3fff
[    0.808773@0] meson-mmc: emmc: err: wait for desc write back, bus_fsm:0x7
[    0.815562@0] meson-mmc: Command retried failed line:585, cmd:1
[    0.821212@3] cectx ff80023c.aocec: cec driver date:Ver 2019/1/7
[    0.821212@3]
[    0.821598@1] cectx ff80023c.aocec: not find 'port_num'
[    0.821601@1] cectx ff80023c.aocec: using cec:1
[    0.821625@1] cectx ff80023c.aocec: no hdmirx regs
[    0.821627@1] cectx ff80023c.aocec: no hhi regs
[    0.821632@1] cectx ff80023c.aocec: not find 'output'
[    0.823090@1] cectx ff80023c.aocec: irq cnt:2
[    0.834298@1] cectx ff80023c.aocec: wakeup_reason:0x0
[    0.843569@4] cectx ff80023c.aocec: cev val1: 0x0;val2: 0x0
[    0.843571@4] cectx ff80023c.aocec: aml_cec_probe success end
[    0.872115@4] defendkey ff630218.defendkey: Reserved memory is not enough!
[    0.879396@1] Amlogic A/V streaming port init
[    0.882218@2] Error: Driver 'spdif-dit' is already registered, aborting...
[    0.882997@2] aml_card_probe error ret:-517
[    1.402794@3] meson-mmc: card IN
[    1.709780@3] meson-mmc: Tuning transfer error: nmatch=0 tuning_err:0xffffffac
CoreELEC:~ # pwr_key=23dc4db2
usr_ir_proto = 00000000
wake-on-lan = 00000001
[   66.987692@0] reboot: Restarting system
bl31 reboot reason: 0xd
bl31 reboot reason: 0x1
system cmd  1.
G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.4
           bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
B2:00002000
B1:e0f83180

TE: 415034

BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz

Board ID = 4
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00069dcb
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15
board id: 4
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==94 ps 8
R0_TxDqDly_Margi==118 ps 10


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001

 ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 1024MB
DMC_DDR_CTRL: 0060001bDDR size: 2048MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass
 pre test  bdlr_100_average==445 bdlr_100_min==445 bdlr_100_max==445 bdlr_100_cur==445
 aft test  bdlr_100_average==445 bdlr_100_min==445 bdlr_100_max==445 bdlr_100_cur==445
100bdlr_step_size ps== 440
result report
boot times 28Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0003c200, des: 0x0172c000, size: 0x00094000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
E30HDR
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz]
OPS=0x40
ring efuse init
chipver efuse init
29 0a 40 00 01 28 12 00 00 17 34 37 57 4e 4b 50
[3.743544 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):ab8811b
NOTICE:  BL31: Built : 15:03:31, Feb 12 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2015.01 (May 09 2019 - 00:42:58)

DRAM:  2 GiB
Relocation Offset is: 76efa000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 0000000077f86848
MMC:   aml_priv->desc_buf = 0x0000000073eea7c0
aml_priv->desc_buf = 0x0000000073eecb00
SDIO Port B: 0, SDIO Port C: 1
Using default environment

In:    serial
Out:   serial
Err:   serial
vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
vpu: clk_level = 7
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_clk_gate_init_off finish
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs_config_hdmipll_g12a
cvbs_set_vid2_clk
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x2000
[mmc_startup] mmc refix success
[mmc_init] mmc init success
reading boot-logo-1080.bmp.gz
30176 bytes read in 7 ms (4.1 MiB/s)
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]set initrd_high: 0x3d800000
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3d800000 width=5760, height=2160
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 2.0  div=10
set hdmitx VIC = 16
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6  vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 16
enc_vpu_bridge_reset[1312]
rx version is 2.0  div=10
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
Net:   dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- :  0
reading boot.ini
2360 bytes read in 3 ms (767.6 KiB/s)
cfgload: applying boot.ini...
cfgload: setenv bootrootfs "BOOT_IMAGE=kernel.img boot=UUID=2404-0631 disk=UUID=d1e6f1fc-2b6b-4bb2-88c9-e4b83bc83482"
cfgload: setenv condev "console=ttyS0,115200 console=tty0"
cfgload: setenv hdmimode "1080p60hz"
cfgload: setenv bmp_width "1920"
cfgload: setenv bmp_height "1080"
cfgload: setenv vout_mode "hdmi"
cfgload: setenv hdmioutput   "1"
cfgload: setenv vpu          "1"
cfgload: setenv coreelec "quiet"
cfgload: setenv hdmi_cec "1"
cfgload: setenv maxcpus "6"
cfgload: setenv max_freq_a73 "1800"
cfgload: setenv max_freq_a53 "1896"
cfgload: setenv rtc_shield "0"
cfgload: setenv emmc_timeout "0"
cfgload: setenv wol "1"
cfgload: setenv remotewakeup "0x23dc4db2"
cfgload: setenv decode_type "0"
cfgload: setenv loadaddr 0x11000000
cfgload: setenv dtb_mem_addr 0x1000000
cfgload: setenv uenv_addr 0x13000000
cfgload: fatload mmc ${mmc_dev}:1 ${loadaddr} kernel.img
reading kernel.img
13862912 bytes read in 756 ms (17.5 MiB/s)
cfgload: fatload mmc ${mmc_dev}:1 ${dtb_mem_addr} dtb.img
reading dtb.img
69212 bytes read in 7 ms (9.4 MiB/s)
cfgload: if fatload mmc ${mmc_dev}:1 ${uenv_addr} config.ini; then env import -t ${uenv_addr} $filesize; fi
reading config.ini
5122 bytes read in 4 ms (1.2 MiB/s)
cfgload: if test "${emmc_timeout}" = "1"; then showlogo ${hdmimode} ${bmp_width} ${bmp_height} timeout-logo-${bmp_height}.bmp.gz; sleep 30; mmc dev 1; mmc dev 0; fi
cfgload: setenv irsetup "hk-lirc-helper.remotewakeup=${remotewakeup} hk-lirc-helper.decode_type=${decode_type}"
cfgload: setenv device "no_console_suspend logo=osd0,loaded,0x3f800000,${hdmimode} vout=${hdmimode},enable voutmode=${vout_mode} hdmimode=${hdmimode} cvbsmode=nocvbs mac=${ethaddr} consoleblank=0 max_freq_a53=${max_freq_a53} max_freq_a73=${max_freq_a73} maxcpus=${maxcpus} enable_wol=${wol}"
cfgload: if test "${hdmi_cec}" = "1"; then setenv cec "hdmitx=cec3f"; fi
cfgload: setenv bootargs "${condev} ${bootrootfs} ${device} ${cec} ${coreelec} ${irsetup}"
cfgload: bootm start
## Booting Android Image at 0x11000000 ...
load dtb from 0x1000000 ......
cfgload: bootm loados
   Uncompressing Kernel Image ... OK
   kernel loaded at 0x01080000, end = 0x0279ea00
cfgload: bootm fdt
   reserving fdt memory region: addr=1000000 size=11000
   Loading Device Tree to 0000000073ed4000, end 0000000073ee7e5b ... OK
cfgload: if test "${vpu}" = "0"; then fdt rm /mesonstream; fdt rm /vdec; fdt rm /ppmgr; fi
cfgload: if test "${hdmioutput}" = "0"; then fdt rm /mesonfb; fi
cfgload: if test "${rtc_shield}" = "1"; then fdt set "/i2c@c1108500/pcf8563@51" status okay; else fdt set "/i2c@c1108500/pcf8563@51" status disabled; fi
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
cfgload: fdt rm /partitions
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
cfgload: bootm prep
   reserving fdt memory region: addr=1000000 size=11000
   Loading Ramdisk to 3d454000, end 3d7ffe00 ... OK
   Loading Device Tree to 0000000073ebd000, end 0000000073ed3e5b ... OK
cfgload: bootm go

Starting kernel ...

uboot time: 7491053 us
[    0.323113@0] codec_mm_module_init
[    0.331039@0] clkmsr ffd18004.meson_clk_msr: failed to get msr ring reg0
[    0.347034@0] cvbs_out: chrdev devno 263192576 for disp
[    0.470471@2] dmi: Firmware registration failed.
[    0.530330@2] perf_event: read sys_cpu_status0_offset failed, ret = -22
[    0.543244@4] meson-pwm ff802000.pwm: pwm pinmux : can't get pinctrl
[    0.543465@4] meson-pwm ffd1b000.pwm: pwm pinmux : can't get pinctrl
[    0.550317@4] mtdoops: mtd device (mtddev=name/number) must be supplied
[    0.565619@4] meson_cpufreq_probe: Registered platform drive
[    0.565736@4] ff803000.serial: clock gate not found
[    0.617878@4] gpio-keypad ff800000.gpio_keypad: failed to get gpio index from dts
[    0.623971@4] efuse efuse:  open efuse clk gate error!!
[    0.630917@2] amvideocap_probe,amvideocap
[    0.632995@2] use cma buf.
[    0.636211@2] fb: failed to init reserved memory
[    0.684760@2] di_get_vpu_clkb: get clk vpu error.
[    0.685798@2] PPMGRDRV: err: ppmgr_driver_probe called
[    0.688970@2] Reserved memory: failed to init DMA memory pool at 0x0000000075800000, size 0 MiB
[    0.699312@3] meson-mmc: >>>>>>>>hostbase ffffff800863d000, dmode
[    0.752615@0] meson-mmc: emmc: resp_timeout,vstat:0xa1ff2800,virqc:3fff
[    0.753591@0] meson-mmc: emmc: err: wait for irq service, bus_fsm:0x8
[    0.760036@1] meson-mmc: meson_mmc_irq_thread_v3() 567: set 1st retry!
[    0.766531@1] meson-mmc: retry cmd 1 the 3-th time(s)
[    0.771985@0] meson-mmc: >>>>>>>>hostbase ffffff8008688000, dmode
[    0.777754@0] meson-mmc: emmc: resp_timeout,vstat:0xa1ff2800,virqc:3fff
[    0.777755@0] meson-mmc: emmc: err: wait for irq service, bus_fsm:0x8
[    0.777774@1] meson-mmc: retry cmd 1 the 2-th time(s)
[    0.790755@0] meson-mmc: emmc: resp_timeout,vstat:0xa1ff2800,virqc:3fff
[    0.790757@0] meson-mmc: emmc: err: wait for irq service, bus_fsm:0x8
[    0.790767@1] meson-mmc: retry cmd 1 the 1-th time(s)
[    0.791760@0] meson-mmc: emmc: resp_timeout,vstat:0xa1ff2800,virqc:3fff
[    0.791762@0] meson-mmc: emmc: err: wait for irq service, bus_fsm:0x8
[    0.791770@1] meson-mmc: Command retried failed line:585, cmd:1
[    0.873162@2] cectx ff80023c.aocec: cec driver date:Ver 2019/1/7
[    0.873162@2]
[    0.875484@2] cectx ff80023c.aocec: not find 'port_num'
[    0.880399@2] cectx ff80023c.aocec: using cec:1
[    0.884901@2] cectx ff80023c.aocec: no hdmirx regs
[    0.889671@2] cectx ff80023c.aocec: no hhi regs
[    0.894175@2] cectx ff80023c.aocec: not find 'output'
[    0.900636@2] cectx ff80023c.aocec: irq cnt:2
[    0.903690@2] cectx ff80023c.aocec: wakeup_reason:0x0
[    0.908621@2] cectx ff80023c.aocec: cev val1: 0x0;val2: 0x0
[    0.914100@2] cectx ff80023c.aocec: aml_cec_probe success end
[    0.922569@2] defendkey ff630218.defendkey: Reserved memory is not enough!
[    0.931881@2] Amlogic A/V streaming port init
[    0.934007@3] Error: Driver 'spdif-dit' is already registered, aborting...
[    0.938754@3] aml_card_probe error ret:-517
[    1.075682@2] meson-mmc: card IN
[    1.381669@2] meson-mmc: Tuning transfer error: nmatch=0 tuning_err:0xffffffac
[   37.192179@0] reboot: Restarting system
bl31 reboot reason: 0xd
bl31 reboot reason: 0x1
system cmd  1.
G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.
          bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
B2:00002000
B1:e0f83180

TE: 466844

BL2 Built : 18:57:07, Apr 24 2019. g12b g2c12fac - jenkins@walle02-sh

Board ID = 4
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 000766cf
DDR driver_vesion: LPDDR4_PHY_V_0_1_12 build time: Apr 24 2019 18:57:02
board id: 4
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==118 ps 10
R0_TxDqDly_Margi==70 ps 6


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001

soc_vref_reg_value 0x 00000055 00000055 00000054 00000055 00000053 00000052 00000054 00000055 00000056 00000053 00000056 00000055 00000052 00000053 00000053 00000055 00000056 00000056 00000055 00000054 00000056 00000055 00000055 00000055 00000055 00000053 00000054 00000054 00000053 00000054 00000053 00000055 dram_vref_reg_value 0x 00000049
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 1024MB
DMC_DDR_CTRL: 0060001bDDR size: 2048MB
cs0 DataBus test pass
cs1 DataBus test pass
  ADDR2-W[0x40000000]:0x55555555,R:0x00aaaaaa
cs0 AddrBus test failed
fail address pin cs 0   add 0x 40000000   ra15
cs1 AddrBus test pass
All ddr config failed...
Reset...
boot times 29G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.4
                        bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
B2:00002000
B1:e0f83180

TE: 126123

BL2 Built : 18:57:07, Apr 24 2019. g12b g2c12fac - jenkins@walle02-sh

Board ID = 4
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 000233de
DDR driver_vesion: LPDDR4_PHY_V_0_1_12 build time: Apr 24 2019 18:57:02
board id: 4
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==106 ps 9
R0_TxDqDly_Margi==70 ps 6


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001

soc_vref_reg_value 0x 00000055 00000055 00000054 00000055 00000053 00000052 00000054 00000055 00000056 00000053 00000056 00000055 00000052 00000054 00000052 00000054 00000056 00000056 00000055 00000055 00000056 00000055 00000055 00000055 00000055 00000053 00000054 00000054 00000054 00000054 00000054 00000054 dram_vref_reg_value 0x 0000004a
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 1024MB
DMC_DDR_CTRL: 0060001bDDR size: 2048MB
cs0 DataBus test pass
cs1 DataBus test pass
  ADDR2-W[0x40000000]:0x55555555,R:0x00aaaaaa
cs0 AddrBus test failed
fail address pin cs 0   add 0x 40000000   ra15
cs1 AddrBus test pass
All ddr config failed...
Reset...
boot times 30G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0
                        bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
B2:00002000
B1:e0f83180

TE: 126149

BL2 Built : 18:57:07, Apr 24 2019. g12b g2c12fac - jenkins@walle02-sh

Board ID = 4
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 000233f8
DDR driver_vesion: LPDDR4_PHY_V_0_1_12 build time: Apr 24 2019 18:57:02
board id: 4
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==106 ps 9
R0_TxDqDly_Margi==82 ps 7


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001

soc_vref_reg_value 0x 00000056 00000056 00000054 00000056 00000053 00000053 00000054 00000055 00000056 00000054 00000056 00000055 00000051 00000054 00000053 00000054 00000056 00000056 00000055 00000054 00000056 00000054 00000055 00000054 00000055 00000053 00000054 00000053 00000053 00000054 00000053 00000054 dram_vref_reg_value 0x 0000004a
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 1024MB
DMC_DDR_CTRL: 0060001bDDR size: 2048MB
cs0 DataBus test pass
cs1 DataBus test pass
  ADDR2-W[0x40000000]:0x55555555,R:0x00aaaaaa
cs0 AddrBus test failed
fail address pin cs 0   add 0x 40000000   ra15
cs1 AddrBus test pass
All ddr config failed...
Reset...
boot times 31G