Dtb image for beelink gt king pro?

Hello,
Is there a dtb for the gt king pro? The gpu speed is rated for 843Mhz but the generic beelink gt king locks the gpu frequency at 800Mhz.

Could we perhaps manually set the gpu frequency in /flash/config.ini?

see:

I think you talk about RAM clock speed and not CPU clock speed. The RAM speed can not be changed as it’s hardcoded by the bootloader. There is no real “GPU”.

You are able to overclock the CPU by config.ini, yes.

EDIT:
I am sorry, maybe I was wrong. There is a gpu clock in the dts:

But it include already 850 with a clock of 846000000Hz.
But no idea where and who does choose it.

1 Like

Hey, I decompiled the dtb file and found below. When I remove the first tbl entry when the device loads it’s max_freq shows 3 instead of 4, and still defaulting cur_freq to 800Mhz.

cat /sys/class/mpgpu/cur_freq // shows 800
cat /sys/class/mpgpu/max_freq // shows 4 normally, and 3 when first table entry removed.

So I guess what I need to know is what entry in the dtb file do I change so it loads the last table entry, 0x7E ?

	bifrost {
		compatible = "arm,malit60x\0arm,malit6xx\0arm,mali-midgard";
		#cooling-cells = <0x02>;
		reg = <0x00 0xffe40000 0x00 0x4000 0x00 0xffd01000 0x00 0x1000 0x00 0xff800000 0x00 0x1000 0x00 0xff63c000 0x00 0x1000 0x00 0xffd01000 0x00 0x1000>;
		interrupt-parent = <0x01>;
		interrupts = <0x00 0xa0 0x04 0x00 0xa1 0x04 0x00 0xa2 0x04>;
		interrupt-names = "GPU\0MMU\0JOB";
		num_of_pp = <0x02>;
		sc_mpp = <0x01>;
		clocks = <0x02 0x83 0x02 0x07>;
		clock-names = "gpu_mux\0gp0_pll";
		tbl = <0x03 0x04 0x05 0x06 0x07 0x07e>;
		system-coherency = <0x00>;
		phandle = <0x7b>;

		clk125_cfg {
			clk_freq = <0x7735940>;
			clk_parent = "fclk_div4";
			clkp_freq = <0x1dcd6500>;
			clk_reg = <0xa03>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0x1e 0x78>;
			phandle = <0x7c>;
		};

		dvfs250_cfg {
			clk_freq = <0xee6b280>;
			clk_parent = "fclk_div4";
			clkp_freq = <0x1dcd6500>;
			clk_reg = <0xa01>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0x50 0xaa>;
			phandle = <0x7d>;
		};

		dvfs285_cfg {
			clk_freq = <0x1107a76d>;
			clk_parent = "fclk_div7";
			clkp_freq = <0x1107a76d>;
			clk_reg = <0xe00>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0x64 0xbe>;
			phandle = <0x03>;
		};

		dvfs400_cfg {
			clk_freq = <0x17d78400>;
			clk_parent = "fclk_div5";
			clkp_freq = <0x17d78400>;
			clk_reg = <0xc00>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0x98 0xcf>;
			phandle = <0x04>;
		};

		dvfs500_cfg {
			clk_freq = <0x1dcd6500>;
			clk_parent = "fclk_div4";
			clkp_freq = <0x1dcd6500>;
			clk_reg = <0xa00>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0xb4 0xdc>;
			phandle = <0x05>;
		};

		dvfs666_cfg {
			clk_freq = <0x27bc86aa>;
			clk_parent = "fclk_div3";
			clkp_freq = <0x27bc86aa>;
			clk_reg = <0x800>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0xd2 0xec>;
			phandle = <0x06>;
		};

		dvfs800_cfg {
			clk_freq = <0x2faf0800>;
			clk_parent = "fclk_div2p5";
			clkp_freq = <0x2faf0800>;
			clk_reg = <0x600>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0xe6 0xff>;
			phandle = <0x07>;
		};

		dvfs850_cfg {
			clk_freq = <0x326cef80>;
			clk_parent = "gp0_pll";
			clkp_freq = <0x326cef80>;
			clk_reg = <0x200>;
			voltage = <0x47e>;
			keep_count = <0x05>;
			threshold = <0xe6 0xff>;
			phandle = <0x7e>;
		};
	};

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