It’s not a matter of having problems, I don’t (apart from the second box I bought frying its HDMI output after two days, as outlined above).
It’s just that a faster clock on the two big cores could result in snappier performance and I simply want to understand if the current configuration is simply left over from old S922X chips or if it’s a conscious decision for whatever reason.
EDIT: if you check here: Amlogic - Wikipedia you can see that the clocks are configured as if the box was using a S922X and not a S922XJ.
Hmmm… although the code I posted from dispinfo appears to me remmed out, so maybe all is good. Hope to get confirmation on this.
EDIT 2: Found out all is good, using lscpu this is the output:
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 6
On-line CPU(s) list: 0-5
Vendor ID: ARM
Model name: Cortex-A53
Model: 4
Thread(s) per core: 1
Core(s) per socket: 2
Socket(s): 1
Stepping: r0p4
CPU(s) scaling MHz: 100%
CPU max MHz: 1800.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32
Model name: Cortex-A73
Model: 2
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
Stepping: r0p2
CPU(s) scaling MHz: 100%
CPU max MHz: 2208.0000
CPU min MHz: 500.0000
BogoMIPS: 48.00
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32